1. Field of the Invention
The present invention relates to an electrical fuse determination circuit and a determination method that are preferably employed in a semiconductor memory and a semiconductor device having the semiconductor memory.
Priority is claimed on Japanese Patent Application No. 2007-286414, filed Nov. 2, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
In a conventional semiconductor memory, when a memory cell of a failure operation is detected during a test process before a product delivery, the circuit operation is generally switched to the operation that uses a preliminary memory cell (redundancy cell). In this operation of switching to a redundancy cell, it is generally carried out that a laser beam is irradiated to a preformed circuit line for fusing so as to take fusion cutting of the circuit line of a wafer before package assembly. Since this fusion cutting of the circuit line for fusing can be achieved only before package assembly, an electrical fuse that can change the circuit operation even after package assembly has been used in recent semiconductor memory (alternately, the cutting fuse by the laser beam and the electrical fuse are used together).
The electrical fuse is called an anti fuse, and is a non-conductive device in the initial state and composed of an insulator sandwiched between two electrodes. When a high voltage is applied between the two electrodes of the electrical fuse device, the insulator is broken down. Thereby, the electrodes connect (short) with each other so as to assume the conductive state. Accordingly, even after package assembly, it is possible to change the desired electrical fuse into the connecting (conductive) state through inputting a specific signal from the outside. Therefore, even when a failure cell is detected after package assembly, it is possible to plan an enhancement of the yield by using the electrical fuse and substituting the redundancy cell.
Connect information, in which whether a plurality of the electrical fuses provided in the semiconductor device assumes the conductive or non-conductive state, is incorporated into the device inside by a determination circuit when the power supply turns on, the specific circuit operation occurs based on the connect information.
FIG. 3 shows an example of an electric fuse determination circuit according to a related art. This circuit is assumed to be formed in a synchronous dynamic random access memory (DRAM). Reference symbols 21 through 27 correspond to a p-channel metal oxide semiconductor (PMOS) transistor, reference symbols 28 through 34 correspond to an n-channel metal oxide semiconductor (NMOS) transistor, and reference symbols 35 and 36 correspond to an electrical fuse device. A signal Vpp_ov normally corresponds to a Vdd level (power supply voltage level), while the signal Vpp_ov is higher than the Vdd level when the electrical fuse assumes the conductive state. A signal Vbb_ud normally corresponds to a Vss level (ground voltage level), while the signal Vbb_ud is lower than the Vss level when the electrical fuse assumes the conductive state. A control signal STORE puts the electrical fuse in the conductive state, a control signal LOAD incorporates electrical fuse data, a reference voltage is a voltage of middle level lower than the Vdd level, a node A corresponds to a contact node of the electrical fuse device, and a control signal PRE precharges the node A with the Vdd,
Subsequently, the connect operation of the electrical fuse will be described hereinbelow. In the case of the electrical fuse being connected, the signal STORE is placed into an “L” state so that the Vpp_ov and the Vbb_ud levels are applied to both contact points of the electrical fuse devices 35 and 36. Thereby, the electrical fuse devices 35 and 36 are broken down so as to assume the conductive state.
Then, the incorporate operation of the electrical fuse data will be described hereinbelow. The signal PRE generates a one-shot “L” pulse through a mode register set command MRS. By this one-shot pulse, the PMOS transistor 27 is turned on and the node A is precharged with the Vdd. When the signal PRE is placed into an “H” state, the node A is pulled down to the Vss level through the electrical fuse devices 35 and 36. After a predetermined period elapses from the signal PRE being placed into an “H” state, one-shot pulse of the signal LOAD is generated. By this one-shot pulse of the signal LOAD, levels of the node A and the reference voltage are compared, the determination result is output, and hence, the electrical fuse data is incorporated.
Subsequently, an operation of the electrical fuse determination circuit will be described hereinbelow. FIG. 4 shows a timing chart after the command MRS of the electrical fuse determination circuit shown in FIG. 3 is input. A reference symbol CK corresponds to an external clock signal CLK. The one-shot pulses of the signal PRE and the signal LOAD are generated within 2 clock periods (tMRD=2CLK) after the command MRS is input. The level of the node A is precharged with the Vdd through the signal PRE. After that, the level of the node A is decrease. The one-shot pulse of the signal LOAD is generated when the level of the node A becomes lower than the reference voltage. A determination circuit made of the NMOS transistors 32, 33, 34, and the like, outputs a determination result, in which the level of the node A is lower than the reference voltage, so as to incorporate the electrical fuse data.
When the insulator used in the electrical fuse device is broken down through the high voltage applied to the electrical fuse device so as to assume the conductive state, the electrical resistance value thereof under conductive state frequently fluctuates. Therefore, for example, as shown in FIG. 3, a circuit is provided that includes two electrical fuse devices connected in parallel having the same configuration and further includes the same circuit portions that apply the high voltage. When the electrical fuse device assumes the conductive state, both electrical fuse devices connected in parallel assume the conductive state. In this manner, the fluctuation of the electrical resistance value is suppressed.
However, as with the dotted line shown in FIG. 4, since the resistance of the electrical fuse is high, even if the level of the node A does not decrease below the reference voltage during the period from the signal PRE being placed into an “H” state to the signal LOAD being placed into an “H” state, the determination circuit outputs the determination result, in which the level of the node A is higher than the reference voltage, so as to fail to incorporate the electrical fuse data. Since there is only a period of the 2CLK from the command MRS to a bank active command ACT, a timing margin becomes small if the resistance of the electrical fuse is high under conductive state.
Therefore, according to the electrical fuse determination method, when the resistance of the electrical fuse becomes high under conductive state due to the fluctuation thereof during the production, the conductive state of the electrical fuse cannot be determined, and hence, there has been a problem in which the semiconductor device does not operate as desired (substituting a redundancy cell, and the like). As a result, there has been a problem that decreases the yield of the semiconductor device during the production.
In FIG. 3, the reference symbol tMRD corresponds to a load mode command cycle time, and the reference symbol tRCD corresponds to an active command read/write command delay. The reference symbol WR/RD indicates the read/write command. The NMOS transistors 32 and 33 compose an input portion of a comparator circuit taking the reference voltage as a reference level thereof. The PMOS transistors 25 and 26 are controlled to turn off when the electrical fuse devices 35 and 36 assume the conductive state (during programming), while the PMOS transistors 25 and 26 are controlled to turn on when the electrical fuse data is incorporated. The PMOS transistors 25 and 26 are employed to disconnect from the other electrical fuse device and the circuit when the electrical fuse device assumes conductive state.
The prior art is disclosed in Published Japanese translation of a PCT application No. 2000-512059, and Japanese Unexamined Patent Application, First Publication, No. 2001-067893 and No. 2006-339290.
Then are several problems in the electrical fuse determination circuit.
A first problem is that the incorporation of the electrical fuse data takes an error, when the resistance of the electrical fuse cannot be decreased enough. The reason for this problem is attributed to a time limitation from the command MRS to the command ACT, since the electrical fuse data is incorporated by the command MRS.
Conventionally, at the time of inputting the command MRS, the node connecting with the electrical fuse device (node A shown in FIG. 3) starts precharging so as to pull up the voltage thereof to the Vdd level. Then, if the electrical fuse device assumes the conductive state, the voltage of the node decreases to the Vss level. When the conductive resistance of the electrical fuse device is higher than a predetermined value, the voltage of the node does not decrease enough until the time of determining the node state so as to take an error of determination.
A second problem is that the reliability of the electrical fuse device is degraded in use. The reason for this problem is attributed to the electrical fuse device assuming the conductive state pulling down the node A to the Vss level after precharging to the Vdd level while incorporating data thereof, and hence, the current flows through the electrical fuse device.
The electrical fuse device, which assumes the conductive state, conducts through a current path like a pin hole formed by breaking the insulator down. Thereby, the current density is much higher than that in the conventional circuit line. Accordingly, even if the current keeps flowing, the current path formed is cut off due to the current stress, or the conductive resistance of the electrical fuse device increases. Therefore, the decreased reliability is apprehended in the conventional electrical fuse device.
Although an occurrence of the deficiency which is caused by the problems described above is suppressed through two electrical fuse devices connected in parallel to assume the same conductive state in the prior art, that is not the complete countermeasure.